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NXP Semiconductors /LPC18xx /CGU /PLL0USB_NP_DIV

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Interpret as PLL0USB_NP_DIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDEC0RESERVED0NDEC0RESERVED

Description

PLL0USB N/P-divider register

Fields

PDEC

Decoded P-divider coefficient value
RESERVED

Reserved
NDEC

Decoded N-divider coefficient value
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data